Realisation and Test of Digital Components

Design methodology. Automated and manual synthesis of digital modules and components. Realisation with standard cells or FPGAs. Use of integrated EDA systems. Timing analysis. Partitioning, placement and routing. Test issues: fault models, test generation, fault simulation, Design for Testability, BIST, test quality, test economics. Test equipment and test standards.

Knowledge:
Obtain knowledge and experience with methods for realisation and test of digital components.

Skills:
Gain skills in electronic lab, and in use of state-of-the-art EDA tools.

Lectures, self study, project and lab assignments. Written exam counts 60%, project counts 25% and lab counts 15% of the final grade. If there is a re-sit examination, the examination form may be changed from written to oral. The course is given in English.