Design of Digital Systems 2

This course deals with the challenges when developing complex digital systems such as a System-on-Chip (SoC). Focus is on advanced methods, notations and languages, tools and systems, high level (abstract) description and communication, simulation, and verification including UVM (Universal Verification Methodology). Verification will receive the highest focus.

Subjects are System On Chip as definition and the challenges in developing such, and also the system decription languages used for that purpose. For verification, both high level description and assertion based verification in SystemVerilog and UVM, and also formal verification with model checking is used.

Term project: The use of high level design tools for description, simulation, verification and implementation.

Knowledge: The candidate has

• detailed understanding of what characterizes systems-on-chip, how such are specified, designed, implemented and used, and what challenges lies within this.
• advanced knowledge about high level descriptions of complex systems containing both hardware and software.
• profound understanding of the principles in formal and assertion based verification.
• detailed knowledge about the fundamentals and methods for modelling and simulation on system and transaction level.

Skills: The candidate can

• use high level description languages for the design of modules for systems-on-chip or other complex system of hardware and software.
• develop assertion based properties and use such for system level verification.
• describe temporal logic system requirements and prove or disprove such by model checking.

Lectures. Practical/theoretical exercises, and a term project in groups. All laboratory exercises are mandatory and have to be approved for entrance to the exam.